Automated UVM Tuning Orchestrated Via AI Reasoning
Contributor: Abdul_Rehman
Verification in hardware design is a time-consuming and complex task as well as requires manual effort to update UVM testbench components...
Other
Micro Electronics Research Lab - UITU
Accelerating Engineering Innovation
Technologies
HardwarememoryProcessorRISC-Vsystemonchip
Topics
embeddediotProcessorRISC-VSystem on Chip
- Total projects
- 12
- Years participating
- 4
- Most recent
- 2025
Participation history
Historical projects
Integrating TCAM IP into Chipyard via MMIO and RoCC Interfaces
Contributor: Atharva Nerkar
This project focuses on integrating a Ternary Content Addressable Memory (TCAM) module into the Chipyard SoC framework to enable high-speed parallel...
AEGIS - AI-Enhanced Generation of Intelligent Scenarios
Contributor: Mahnoor_Ismail
AEGIS automates hardware verification by using AI to generate optimized test cases. Parses Specifications: Extracts key features (interfaces,...
Running Secure and Vectorized Applications on SoC-Now
Contributor: Muhammad Hussain_017
This project aims to develop and benchmark high-performance applications that leverage the modular SoC-Now platform, which integrates RISC-V cores, a...
PyUVM-Based General Testbench for RISC-V Cores
Contributor: Nitin Grandhi
With the increasing adoption of RISC-V as an open-source Instruction Set Architecture (ISA), there is a growing need for effective and reusable...
Vaquita Vector Coprocessor
Contributor: Mohammad Latif
Summary The project aims to enhance Nucleus RV Core by adding the RISC-V Vector Extension (RVV v1.0) as a co-processor. Key objectives include...
Baby Kyber Accelerator
Contributor: Hamna Mohiuddin
The "Baby Kyber Accelerator" project aims to address the increasing demand for secure communication by developing a specialized hardware accelerator...
ASIC Design of OpenTCAM Generated IPs using OpenLane and GF180/SKY130
Contributor: V Vignesh Karthik
This project involves generating layouts and GDSII files for IPs produced with OpenTCAM, utilising diverse memory structure configurations. TCAM IPs...
TileLink Uncached Heavyweight (TL-UH) implementation in Azadi-SoC
Contributor: Doaa Magdy
In this proposal, I am going to introduce the steps needed to upgrade Tilelink Uncached Lightweight (TL-UL) bus protocol to TL-UH (Tilelink Uncached...
Development of a Python compiler for a resource-efficient SRAM-based TCAM
Contributor: Usman Siddique
TCAM is used to search contents stored in memory. Although it is faster compared to SRAM it has disadvantages including increased size, higher energy...
Add FuseSoC support at SoC level for Azadi-SoC and Rebase ibex core with the latest commit.
Contributor: NAMEER IQBAL ANSARI.
The project aims to “Add FuseSoC support at SoC level for Azadi-SoC and Rebase ibex core with the latest commit”. As currently, The ibex core used in...
Integration of Compressed (C) extension in NucleusRV core
Contributor: Abdul Wadood
The project deals with the integration of RISC-V Compressed Extension into the NucleusRV core. For most embedded processors, the size of programmable...