Support Zvk in T1 (RISC-V Vector coprocessor)
Contributor: Syed Hassan Ul Haq
Our "Support Zvk in T1" project aims to upgrade the T1 processor by adding Zvk, a cryptographic feature from the RISC-V architecture, enhancing its...
Programming languages
CHIPS Alliance
Open source IP, tools & standards for ASIC/FPGA
Technologies
ASICchiselfpgaRISC-Vsystemverilog
Topics
ASIC designchipletsHDLIP coressoc
- Total projects
- 12
- Years participating
- 3
- Most recent
- 2024
Participation history
Historical projects
Create a GDS reader/writer in OpenROAD
Contributor: Muddassir Ali Siddiqui
I, Muddassir Ali, a final-year Computer Systems Engineering undergraduate student from Pakistan, aim to contribute to the OpenROAD project by...
Relational Framework for Prompt-based Automatic Layout Generation with Glayout
Contributor: Chetanya Goyal
The proposal seeks to build upon an existing relational framework that facilitates the generation of DRC-compliant analog layouts through...
GDS Reader/Writer in OpenROAD
Contributor: Fangzhong (Barry) Lyu
This Project adds GDS input and output features to OpenRoad. It would replace the current GDS manipulation scheme, which is through Klayout, and...
Implement Zc RISC-V ISA Extension in Rocket Chip
Contributor: Abdul Wadood
This project aims to add support for the RISC-V Code size reduction extension (Zcb, Zcmp, Zcmt) to Rocket Core and perform the architectural testing...
DSP hard block integration in F4PGA
Contributor: Abhishek_Anand
F4PGA is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. Currently,...
1st CLasS (Custom Logic as a Service) for Local FPGA Deployment using F4PGA
Contributor: Ali Sajjad
1st CLasS framework is an open-source project that deals with the deployment of a custom kernel on AWS EC2 instance cloud FPGAs with fully automated...
Implementation of a Common Python Framework for OpenFASoC Generators
Contributor: Harsh Khandeparkar
OpenFASoC is a project focused on creating fully automated user specifications to GDS generation flow using open-source tools. OpenFASoC uses tools...
Makerchip Flows: A Suite of EDA Flow integrations for TL-Verilog ecosystem
Contributor: Shrihari
Makerchip Flows aims at developing EDA flows for TL-Verilog leveraging Edalize backend, for open source tools/flows like yosys, Openlane, F4PGA,...
Verible SystemVerilog Preprocessor
Contributor: Karim Tera
The objective is to create a SystemVerilog preprocessor for Verible (which is a suite of SystemVerilog developer tools, including a parser,...
Improving the automatic layout generation of the mixed-signal temperature sensor block in OpenFASOC
Contributor: Lucca Silva
OpenFASOC is an open-source framework for autonomous generation of optimized integrated circuit blocks given user specifications. It is a growing...
Development of a smart CI workflow to test analog block functionality and performance in OpenFASOC
Contributor: saicharan00112
OpenFASOC, an automated SOC generator, is enabling chip enthusiasts to develop circuits/macros with a software approach. Circuits must not only be...